1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and more particularly relates to an insulated gate semiconductor device having improved detection accuracy with a sensing transistor which perform current detection in a main transistor.
2. Description of the Related Art
As a conventional insulated gate semiconductor device, there has been known an insulated gate semiconductor device in which a transistor and a sensing transistor are integrated into one chip. The transistor performs main operations and the sensing transistors perform current detection and the like in the transistor performing the main operations. This technology is described for instance in Japanese Patent Application Publication No. 2002-314086.
FIG. 7 is a plan view showing a MOSFET having a trench structure as an example of the conventional insulated gate semiconductor device. Note that metal electrode layers, such as a source electrode and a gate pad electrode, and an interlayer insulating film are omitted in FIG. 7.
As shown in FIG. 7, a main operation part 41, in which MOS transistors 35m performing main operations are disposed, and a sense part 42, in which sensing MOS transistors 35s are disposed, are integrated in one MOSFET chip. Moreover, channel regions 33 and 34 respectively of the main operation part 41 and the sense part 42 are isolated from each other with a predetermined space therebetween.
A semiconductor substrate 30 is formed, for example, by stacking an n− type semiconductor layer on an n+ type silicon semiconductor substrate, and serves as a drain region. The p type channel regions 33 and 34 are provided in a surface of the n− type semiconductor layer. Moreover, trenches are provided in the channel regions 33 and 34. Gate electrodes are buried in the trenches after the insides of the trenches are covered with insulating films. The MOS transistors 35m and 35s are disposed, for example, in a lattice pattern. The MOS transistors 35m and 35s provided in the respective channel regions 33 and 34 have the same configuration.
In the surface of the n− type semiconductor layer around the channel regions 33 and 34, a guard ring 45 having p+ type impurities diffused therein is disposed as needed. Furthermore, a shield metal 47 is provided in the outermost periphery of the chip.
The gate electrode which drives the sense part 42 is connected to the gate electrode in the main operation part 41 by a gate connection electrode 36 made of polysilicon or the like. A gate pad electrode 44 is provided on the surface of the substrate at a corner portion of the chip (the semiconductor substrate 30) and is connected to the gate connection electrode 36.
Specifically, the MOS transistors 35m and 35s respectively in the main operation part 41 and the sense part 42 are simultaneously driven, and a current is detected in the sense part 42. Thus, abnormalities such as an overcurrent in the main operation part 41 are monitored and controlled.
FIG. 8 is a cross-sectional view schematically showing a current path when the conventional MOSFET is on. FIG. 8 is a cross-sectional view taken along the line d-d in FIG. 7.
An n− type semiconductor layer 32 is stacked on an n+ type semiconductor substrate 31, and then the MOS transistors 35m and 35s are disposed at a cell ratio of, for example, 1000:1 in the respective channel regions 33 and 34 provided in the surface of the n− type semiconductor layer 32. Note that detailed illustration and description of the MOS transistors 35m and 35s are omitted here.
A current flowing into the semiconductor layer 32 from each cell of the MOS transistors 35m and 35s flows so as to spread not only in a vertical direction of the semiconductor layer 32 but also in a horizontal direction. In the drawing, current flows in about 45° direction are indicated by the arrows.
In the semiconductor layer 32 immediately below the channel regions 33 and 34, spreading current paths overlap with each other to form an approximately even current distribution. However, since there is not much overlap in edge portions of the channel regions 33 and 34, the current distribution becomes uneven in the edge portions compared with the vicinities of the centers (immediately below the channel regions 33 and 34).
Since the main operation part 41 which performs the main operation has a number of cells of the MOS transistors 35m, an area of a region immediately below the channel region 33 where the current distribution becomes even (hereinafter referred to as an even region CR1) is also large. Specifically, an area proportion of a region where the current distribution in the edge portion is uneven (hereinafter referred to as an uneven region CR2) is smaller than that of the even region CR1. In other words, the presence of the uneven region CR2 hardly has any influence.
Meanwhile, the sense part 42 has a very small number of the MOS transistors 35s compared with the number of the MOS transistors 35m in the main operation part 41 (for example, 1/1000). Although a region (an even region CR1) immediately below the channel region 34 is small in area, an uneven region CR2 is still generated as in the case of the main operation part 41. Thus, in the sense part 42, an area proportion of the uneven region CR2 to the even region CR1 is large. As a result, influence of the presence of the uneven region CR2 is increased.
In terms of designing, current capacities in proportion to the numbers of cells of the MOS transistors 35m and 35s should be obtained in the main operation part 41 and the sense part 42 respectively. If the respective current distributions are similarly even, on-resistance is also in proportion to the number of cells.
However, as described above, the presence of the uneven region CR2 has a significant influence in the sense part 42. Thus, for example, when comparison is made per unit channel region area (or unit cell), the uneven current distribution is more likely to occur in the sense part 42 than in the main operation part 41. Specifically, in the sense part 42, a problem occurs that the on-resistance is reduced to be lower than the designed value by the uneven current distribution.
FIG. 9 is a graph showing designed V-I characteristics (ideal values) in the main operation part 41 and the sense part 42 and actual V-I characteristics in the main operation part 41 and the sense part 42. The broken lines x and y indicate the characteristics of the ideal values in the main operation part 41 and the sense part 42 respectively, and the solid lines x′ and y′ indicate actual characteristics in the main operation part 41 and the sense part 42, respectively.
As is clear from FIG. 9, there is a problem that the current ratio corresponding to the cell ratio between the main operation part 41 and the sense part 42 cannot be obtained as designed. The problem is caused by the actual reduction of on-resistance in the sense part 42.